1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which in particular has multiple semiconductor elements with gate insulation films with different thicknesses formed on the same semiconductor substrate.
2. Background Information
Generally, with respect to semiconductor devices, miniaturization and high integration is expected. Presently, in order to achieve such miniaturization and high integration of a semiconductor device, an element isolating process in a method of manufacturing a semiconductor device applies more of an STI (shallow trench isolation) method than the generally used LOCOS (local oxidation silicon) method. Furthermore, also for the purpose of miniaturization and high integration of a semiconductor device, a gate oxide (also called a gate insulation film) in a semiconductor element is made to become thinner. As the gate oxide becomes thinner, a power source voltage required becomes lower.
Although the reduction in voltage is accompanied by the miniaturization and high integration of semiconductor devices, semiconductor elements (also known as liquid crystal drivers) that are used to drive a liquid crystal display etc. must adopt a structure in which a conventional high power source voltage and a conventional low power source voltage are used in combination.
However, while a MOS transistor for low voltage (hereinafter to be referred to as low voltage MOS transistor), which is one of the semiconductor elements constructing the liquid crystal driver, needs a thin gate oxide, a MOS transistor for high voltage (hereinafter to be referred to as high voltage MOS transistor), which is another semiconductor element constructing the liquid crystal driver, needs a comparatively thick gate oxide which is about 40 nm.
Examples of a method of forming gate oxides with different thicknesses on the same semiconductor substrate are exhibited in Japanese Laid-Open Patent Application No. 2000-150665 (hereinafter to be referred to as a patent reference 1), Japanese Laid-Open Patent Application No. 2000-200836 (hereinafter to be referred to as a patent reference 2) and Japanese Laid-Open Patent Application No. 2000-246480 (hereinafter to be referred to as a patent reference 3), for instance. In these conventional methods, mainly, a field oxide (also called an element isolating insulation film) is formed by the LOCOS method, after which a heat oxidation treatment is conducted on the entire surface thereof to form a thick gate oxide for a high voltage MOS transistor. Then, a region in which a high voltage MOS transistor is to be formed is covered with a resist, and while using this resist as a mask, the thick gate oxide in a region in which a low voltage MOS transistor is to be formed is removed by wet etching. Then, the resist used as the mask is removed, and a thin gate oxide for a low voltage MOS transistor is formed.
In case of forming gate oxides with different thicknesses on the same semiconductor substrate according to the above-described conventional methods, it is necessary to have a process of removing the thick gate oxide in the region where the low voltage MOS transistor is to be formed, using hydrofluoric acid (HF). However, having the process of removing such thick gate oxide may cause a problem in which the upper part of the field oxide might be etched of as well.
Particularly, in case of forming the field oxide by the STI method and forming the gate oxide by the heat oxidation treatment as above, the etching rate of the embedded oxidation film (i.e. the field oxide) by the hydrofluoric acid will exceed the etching rate of the oxidation film (i.e. the gate oxide), and the upper part of the field oxide will be removed to a significant degree.
As a result, the upper surface of a field region (also called an element isolating region) where the field oxide is formed becomes lower than the upper surface of an active region (also called an element forming region) of the semiconductor substrate.
Under such circumstances, a step may be formed between the active region and the field region, and in the later process when a gate electrode is patterned, a resist used in a photolithographic process is pooled in this step, which can cause a problem in which the gate electrode cannot be patterned normally.
Furthermore, due to this step formed between the active region and the field region, a part of the semiconductor substrate will be exposed, which can cause problems such a hump phenomenon etc. that deteriorates element characteristics, deterioration in the reliability of the gate insulation film, and so forth.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method of manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.